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half-duplex, i coupler ? isolated rs-485 transceiver data sheet adm2483 rev. c document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2004C2013 analog devices, inc. all rights reserved. technical support www.analog.com features rs-485 transceiver with electrical data isolation complies with ansi tia/eia rs-485-a and iso 8482: 1987(e) 500 kbps data rate slew rate-limited driver outputs low power operation: 2.5 ma max suitable for 5 v or 3 v operations (v dd1 ) high common-mode transient immunity: >25 kv/s true fail-safe receiver inputs chatter-free power-up/power-down protection 256 nodes on bus thermal shutdown protection safety and regulatory approvals ul recognition: 2500 v rms for 1 minute per ul 1577 csa component acceptance notice #5a iec 609501 800 v rms (basic), 400 v rms (reinforced) vde certificate of conformity din v vde v 0884-10 (vde v 0884-10): 2006-12 v iorm = 560 v peak operating temperature range: ?40c to +85c applications low power rs-485/rs-422 networks isolated interfaces building control networks multipoint data transmission systems functional block diagram de v dd1 gnd 1 gnd 2 v dd2 txd pv rxd re galvanic isolation a b 04736-001 adm2483 figure 1. general description the adm2483 differential bus transceiver is an integrated, galvanically isolated component designed for bidirectional data communication on balanced, multipoint bus transmission lines. it complies with ansi eia/tia-485-a and iso 8482: 1987(e). using analog devices i coupler technology, the adm2483 combines a 3-channel isolator, a three-state differential line driver, and a differential input receiver into a single package. the logic side of the device is powered with either a 5 v or 3 v supply, and the bus side uses a 5 v supply only. the adm2483 is slew-limited to reduce reflections with improperly terminated transmission lines. the controlled slew rate limits the data rate to 500 kbps. the devices input impedance is 96 k, allowing up to 256 transceivers on the bus. its driver has an active-high enable feature. the driver differential outputs and receiver differential inputs are connected internally to form a differential i/o port. when the driver is disabled or when v dd1 or v dd2 = 0 v, this imposes minimal loading on the bus. an active-high receiver disable feature, which causes the receive output to enter a high impedance state, is provided as well. the receiver inputs have a true fail-safe feature that ensures a logic-high receiver output level when the inputs are open or shorted. this guarantees that the receiver outputs are in a known state before communication begins and at the point when communication ends. current limiting and thermal shutdown features protect against output short circuits and bus contention situations that might cause excessive power dissipation. the part is fully specified over the industrial temperature range and is available in a 16-lead, wide body soic package.
adm2483 data sheet rev. c | page 2 of 20 table of contents specifications ..................................................................................... 3 timing specifications ....................................................................... 4 absol ute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 package characteristics ............................................................... 6 re gulatory information ............................................................... 6 insulation and safety - related specifications ............................ 6 vde v 0884 - 10 insulation characteristics .............................. 7 pin configuration and function descriptions ............................. 8 test circuits ....................................................................................... 9 switching charact eristics .............................................................. 10 typical performance characteristics ........................................... 11 circuit description ......................................................................... 14 electrical isolation ...................................................................... 14 truth tables ................................................................................. 15 power - up/power - down characteristics ................................. 15 thermal shutdown .................................................................... 15 true fail - safe receiver inputs .................................................. 15 magnetic field immunity .......................................................... 15 applications information .............................................................. 17 power_valid input ..................................................................... 17 isolated power supply circuit .................................................. 17 outline dimensions ....................................................................... 18 ordering guide .......................................................................... 18 revision history 11/13 rev. b to rev. c change s to feature s section ............................................................ 1 change s to table 5 ............................................................................ 6 change s to vde v 0884 - 10 insulation characteristics section .... 7 updated outline dimensions ....................................................... 18 changes to ordering guide .......................................................... 18 3/05 rev. a to rev. b change to features ........................................................................... 1 change to package characteristics ................................................. 6 changes to pin function descriptions .......................................... 8 changes to figure 9 and figure 11 ............................................... 10 change to power_valid input section ......................................... 17 changes to figure 30 ...................................................................... 17 changes to ordering guide .......................................................... 18 1 /0 5 rev. 0 to rev. a changes to esd maximum rating specification ........................... 5 10/ 04 revision 0: initial version
data sheet adm24 83 rev. c | page 3 of 20 specifica tions 2.7 v dd1 5.5 v, 4.75 v v dd2 5.25 v , t a = t min to t max , unless otherwise noted. table 1 . parameter min typ max unit test conditions/comments driver differential outputs differential output voltage, v od 5 v r = , see figure 3 2.0 5 v r = 50 ? (rs - 422), see figure 3 1.5 5 v r = 27 ? (rs - 485), see figure 3 1.5 5 v v tst = ? 7 v to + 12 v, v dd1 4.75, see figure 4 |v od | for complementary output states 0.2 v r = 27 ? or 50 ? , see figure 3 common - mode output voltage, v oc 3 v r = 27 ? or 50 ? , se e figure 3 |v oc | for complementary output states 0.2 v r = 27 ? or 50 ? , see figure 3 output short - circuit current, v out = high ? 250 +250 ma ? 7 v v out +12 v outpu t short - circuit current, v out = low ? 2 5 0 +2 5 0 ma ? 7 v v out +12 v logic inputs input high voltage 0.7 v dd1 v txd, de, re , pv input low voltage 0.25 v dd1 v txd, de, re , pv cmos logic input current ( txd, d e , re , pv ) ? 10 + 0.01 + 10 a txd, de , re , pv = v dd1 or 0 v receiver differential inputs differential input threshold voltage, v th ? 200 ? 125 ? 30 mv ? 7 v v cm +12 v input hysteresis 20 mv ? 7 v v cm +12 v input resistance (a, b) 96 150 k ? ? 7 v v cm +12 v input current (a, b) 0.125 ma v in = +12 v ? 0.1 ma v in = ? 7 v rxd logic output output high voltage v dd1 ? 0.1 v i out = 20 a , v a ? v b = 0.2 v v dd1 ? 0.4 v dd1 ? 0.2 v i out = 4 ma, v a ? v b = 0.2 v output low voltage 0.1 v i out = ? 20 a, v a ? v b = ? 0.2 v 0.4 v i out = ? 4 ma, v a ? v b = ? 0.2 v output short - circuit current 7 85 ma v out = gnd or v cc three - state output leakage current 1 a 0.4 v v out 2.4 v power supply curr ent logic side 2.5 ma 4.5 v v dd1 5.5 v, outputs u nloaded, re = 0 v 1.3 ma 2.7 v v dd1 3.3 v, outputs u nloaded, re = 0 v bus side 2.0 ma outputs u nloaded, de = 5 v 1.7 ma outputs u nloaded, de = 0 v common - mode transient immunity 1 25 kv/s txd = v dd1 or 0 v, v cm = 1 kv, transient m agnitude = 800 v 1 common - mode transient immunity is the maximum common - mode voltage slew rate that can be sustained while maintaining specification - compliant operation. v cm is the common - mode potential difference between the logic and bus sides. the tran sient magnitude is the range over which the common mode is slewed. the common - mode voltage slew rates apply to both rising and falling common - mode voltage edges.
adm2483 data sheet rev. c | page 4 of 20 t iming s pecifications 2.7 v dd1 5.5 v, 4.75 v v dd2 5.25 v, t a = t min to t max , unless otherwise noted . table 2 . pa rameter min typ max unit test conditions/comments driver maximum data rate 500 kbps propagation delay , t plh , t phl 250 620 ns r ldiff = 54 ? , c l1 = c l2 = 100 pf, see figure 5 and figure 9 skew , t skew 40 ns r ldiff = 54 ? , c l1 = c l2 = 100 pf, see figure 5 and figure 9 rise/fall time , t r , t f 200 600 ns r ldiff = 54 ? , c l1 = c l2 = 100 pf, see figure 5 and figure 9 enable time 1050 ns r l = 500 ? , c l = 100 pf, see figure 6 and figure 11 disable time 1050 ns r l = 500 ? , c l = 15 pf, see figure 6 and figure 11 receiver propagation delay , t plh , t phl 400 1050 ns c l = 15 pf, see figure 7 and figure 10 differential skew , t skew 250 ns c l = 15 pf, see figure 7 and figure 10 enabl e time 25 70 ns r l = 1 k ? , c l = 15 pf, see figure 8 and figure 12 disable time 40 70 ns r l = 1 k ? , c l = 15 pf, see figure 8 and figure 12 power valid input enable time 1 2 s disable time 3 5 s
data sheet adm24 83 rev. c | page 5 of 20 a bsolute m aximum r atings t a = 25c, unless otherwise noted. all voltages are relative to their respective ground. table 3 . parameter r ating v dd1 ? 0.5 v to +7 v v dd2 ? 0.5 v to +6 v digital i nput voltage ( de, re , t x d ) ? 0.5 v to v dd1 + 0.5 v digital output voltage r x d ? 0.5 v to v dd1 + 0.5 v driver output/receiver input voltage ? 9 v to +14 v esd rating: contact (human body model) (a, b pins) 2 kv operating temperature range ? 40c to + 85c storage temperature range ? 5 5c to +1 50c average output current per pin ? 35 ma to +35 ma ja thermal impedance 73 c/w lead temperature soldering (10 s ec ) 260c vapo r phase (60 s ec ) 215c infrared (15 s ec ) 220c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those ind icated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electrostatic charges a s high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degrada - tion or loss of functionality.
adm2483 data sheet rev. c | page 6 of 20 p ackage c haracteristics table 4 . parameter symbol min typ max unit test conditions resistance (input - out put) 1 r i- o 10 12 ? capacitance (input - output) 1 c i- o 3 pf f = 1 mhz input capacitance 2 c i 4 pf input ic junction -to - case thermal resistance jci 33 c/w thermocouple located at center of package un derside output ic junction - to - case thermal resistance jco 28 c/w thermocouple located at center of package underside 1 device considered a 2 - terminal device: pins 1, 2, 3, 4, 5, 6, 7, and 8 shorted together, and pins 9, 10, 11, 12, 13, 14, 15, and 16 shorted together. 2 input capacitance is from any input data pin to ground. r egulatory i nformation the adm2483 has been approved by the followin g organizations : table 5 . ul 1 csa vde 2 r ecognized under 1577 component recognition program approved under csa component acceptance notice #5a certified according to din v vde v 0884 - 10 (vde v 0884 - 10): 2006- 12 iec 609501 800 vrms (1131 v peak ) basic, 400 v rms (565 v peak ) reinforced. file e214100 file 205078 file 2471900 - 4880 - 0001 1 in accordance with ul1577, each adm2483 is proof tested by applying an insulation test voltage 3000 v rms for 1 sec (current leakage detection limit = 5 a). 2 in accordance with vde v 0884- 10 , each adm2483 is proof tested by applying an insulation test voltage 1050 v peak for 1 sec (partial discharge detection limit = 5 pc). i nsulation and s afety - r elated s pecifications table 6 . parameter symbol value unit conditions rated d ielectric i nsulation v oltage 2500 v rms 1 - minute duration minimum e xternal a ir g ap ( c learance) l(i01) 7.45 min mm measured from input terminals to output terminals, shortest distance through air minimum e xternal t racking ( c reepage) l(i02) 8. 1 min mm measured from input termi nals to output terminals, sh ortest distance along body minimum i nternal g ap ( i nternal c learance) 0.017 min mm insulation distance through insulation tracking r esistance ( c omparative t racking i ndex) cti >175 v din iec 112/vde 0303 part 1 isolation g roup iiia material group ( table 1 in din vde 0110,1/89 )
data sheet adm24 83 rev. c | page 7 of 20 vde v 0884 - 10 i nsulation characteri stics this isolator is suitable for reinforced electrical isolation only within this safety limit data. maintenance of this safety data shall be ensured by means of protective circuits. an asterisk (*) on the physical package denotes vde v 0884- 10 approval for 560 v peak working voltage. table 7 . description symbol characteristic unit installation c lassification per din vde 0110 for r ated m ain s v oltage 150 v rms i to iv 300 v rms i to iii 400 v rms i to ii climatic c lassification 40/ 100 /21 pollution d egree ( table 1 in din vde 0110 ) 2 maximum w orking i nsulation v oltage v iorm 560 v peak input to o utput test v oltage, m ethod b1 v pr 1050 v peak v iorm 1.875 = v pr , 100% p roduction t est ed t m = 1 s ec , p artial d ischarge < 5 pc input -to -o utput t est v oltage, m ethod a (after e nvironmental t ests , s ubgroup 1) v iorm 1.6 = v pr , t m = 60 s ec , p artial d ischarge < 5 pc 896 v peak ( after i nput and/or s afety t est , s ubgroup 2/3) v iorm 1.2 = v pr , t m = 60 s ec , p artial d ischarge < 5 pc v pr 672 v peak highest a llowable o v er voltage (transient o ver voltage, t tr = 10 s ec ) v tr 4000 v peak safety - l imiting v alues ( m aximum v alue a llowed in the e vent of a f ailure. see figure 23. ) case t emperature t s 150 c input c urrent i s, input 265 ma output c urrent i s, output 335 ma insulation r esistance at t s , v io = 500 v r s >10 9 ?
adm2483 data sheet rev. c | page 8 of 20 p in configura tion and function de scriptions 04736-002 nc = no connect adm2483 top view (not to scale) v dd1 1 v dd2 16 gnd 1 1 2 gnd 2 1 15 rxd 3 nc 14 re 4 b 13 de 5 a 12 txd 6 nc 11 pv 7 nc 10 gnd 1 1 8 gnd 2 1 9 1 pin 2 and pin 8 are internally connected. either or both may be used for gnd 1 . pin 9 and pin 15 are internally connected. either or both may be used for gnd 2 . figure 2. pin configuration table 8 . pin function descriptions pin no. mnemonic description 1 v dd1 p ower supply (l ogic s ide ). 2, 8 gnd 1 g round (l ogic s ide ). 3 r x d receive r output d ata. when enabled, if (a ? b) ?30 mv, then rxd = high. if (a ? b) ?200 mv, then rxd = low. this is a tristate output whe n the receiver is disabled, that is , when re is driven high. 4 re receiver enable i nput. this is an active - low input. driving this input low enables the receiver, and driving it high disables the receiver. 5 de driver e nable i nput. driving the input high enables the driver, and driving it low disables the driver. 6 txd transmit data i nput. data to be transmit ted by the driver is applied to this input. 7 pv power_ valid. used during power -up and power - down. see the applications information section. 9, 15 gnd 2 g round (b us s ide ). 10, 11, 14 nc no connect. 12 a noninvert ing d river o utput/ r eceiver i nput. when the driver is disabled , or when v dd1 or v dd2 is powered down, p in a is put in to a high impedance state to avoid overloading the bus. 13 b inverting d river o utput/ r eceiver i nput. when the driver is disabled, or when v dd1 or v dd2 is powered down, pin b is put in to a high impedance state to avoid overloading the bus. 16 v dd2 p ower s upply (bus s ide ) .
data sheet adm24 83 rev. c | page 9 of 20 t est circuits 04736-003 v od v oc r r figure 3 . driver voltage measurement 04736-004 v od3 375 ? 375 ? 60 ? v test figure 4. driver voltage measurement a b r ldiff 04736-005 c l1 c l2 figure 5 . driver propagation delay a s1 r l 0v or 3v b 04736-006 de in de s2 v cc c l v out figure 6 . driver enable/disable a 04736-007 b v out c l re figure 7 . receiver propagation delay c l v out r l s2 v cc +1.5v 04736-008 s1 ? 1.5v re in re figure 8 . receiver enable/disable
adm2483 data sheet rev. c | page 10 of 20 switching characteristics 04736-009 t plh v dd1 0v b a v oh a, b v ol 0.5v dd1 0.5v dd1 t skew = | t plh ? t phl | t f 10% point 10% point 90% point 90% point 1/2vo t r t phl vo figure 9. driver propagation delay, rise/fall timing 04736-010 v oh 0v 0v 1.5v 1.5v v ol a ? b rxd t plh t phl t skew = | t plh ? t phl | figure 10. receiver propagation delay 04736-011 de 2.3v 0.5v dd1 v oh 0v v ol v oh ? 0.5v 0.7v dd1 0.3v dd1 v ol + 0.5v 0.5v dd1 2.3v a, b a, b t zl t zh t lz t hz figure 11. driver enable/disable timing 04736-012 v oh v ol v oh ? 0.5v 0.7v dd1 0.3v dd1 v ol + 0.5v re rxd rxd 0v o/p low o/p high 1.5v 0.5v dd1 1.5v t zl t zh 0.5v dd1 t lz t hz figure 12. receiver enable/disable timing
data sheet adm24 83 rev. c | page 11 of 20 typical performance characteristics 1.6 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 85 25 ? 40 04736-038 temperature ( c) supply current (ma) i dd1 _rcvr_enable @ 5.5v i dd2 _de_enable @ 5.5v figure 13 . unloaded supply current vs. temperature 120 100 80 60 40 20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 04736-014 output voltage (v) output current (ma) figure 14 . output cur rent vs. driver output low voltage ?10 ?30 ?50 ?70 ?90 ?110 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 04736-015 output voltage (v) output current (ma) figure 15 . output current vs. driver output high voltage 0.32 0.30 0.28 0.26 0.24 0.22 0.20 ? 40 80 65 50 35 20 5 ? 10 ? 25 04736-031 temperature ( c) output voltage (v) figure 16 . receiver output low voltage vs. temperature , i = C 4ma 4.78 4.76 4.74 4.72 4.70 4.68 4.66 ? 40 80 65 50 35 20 5 ? 10 ? 25 04736-032 temperature ( c) output voltage (v) figure 17 . receiver outp ut high voltage vs. temperature, i = 4 ma 90 0 10 20 30 40 50 60 70 80 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 04736-013 differential output voltage (v) driver output current (ma) figure 18 . driver output current vs. differential output voltage
adm2483 data sheet rev. c | page 12 of 20 460 440 420 400 380 360 340 85 25 ? 40 04736-034 temperature ( c) time (ns) t p_alh @ v dd1 = v dd2 = 5.0v t p_ahl @ v dd1 = v dd2 = 5.0v t p_blh @ v dd1 = v dd2 = 5.0v t p_bhl @ v dd1 = v dd2 = 5.0v figure 19 . driver propagation delay vs. temperature 800 0 100 200 300 400 500 600 700 85 25 ? 40 04736-035 temperature ( c) time (ns) r cvr prop hl/v dd1 = v dd2 = 5.0v r cvr prop lh/v dd1 = v dd2 = 5.0v figure 20 . receiver propagation delay vs. temperature 04736-022 ch1 5.00v ch2 1.00v ch3 1.00v ch4 5.00v m200ns a ch1 3.10v 1 2 4 t 1.33600s figure 21 . driver/receiver propagation delay high to low 04736-023 ch1 5.00v ch2 1.00v ch3 1.00v ch4 5.00v m200ns a ch1 3.10v 1 2 4 t 360.000ns figure 22 . driver/receiver propagation delay low to high
data sheet adm24 83 rev. c | page 13 of 20 350 300 250 200 150 100 50 0 0 50 100 150 200 04736-024 case temperature ( c) safety-limiting current (ma) bus side logic side figure 23 . thermal derat ing curve, dependence of safety - limiting values with case temperature per vde v 0884 0 ? 30 ? 25 ? 20 ? 15 ? 10 ? 5 5.0 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 04736-036 output voltage (v) output current (ma) figure 24 . output current vs. receiver output high voltage 35 0 5 10 15 20 25 30 2.25 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 04736-037 output voltage (v) output current (ma) figure 25 . output current v s. receiver output low voltage
adm2483 data sheet rev. c | page 14 of 20 circuit description electrical isolation in the adm2483 , electrical isolation is implemented on the logic side of the interface. therefore, the part has two main sections: a digital isolation section and a transceiver section (see figure 26). driver input and data enable signals, applied to the txd and de pins, respectively, and referenced to logic ground (gnd 1 ), are coupled across an isolation barrier to appear at the transceiver section referenced to isolated ground (gnd 2 ). similarly, the receiver output, referenced to isolated ground in the transceiver section, is coupled across the isolation barrier to appear at the rxd pin referenced to logic ground. icoupler technology the digital signals are transmitted across the isolation barrier using i coupler technology. this technique uses chip-scale transformer windings to couple the digital signals magnetically from one side of the barrier to the other. digital inputs are encoded into waveforms that are capable of exciting the primary transformer winding. at the secondary winding, the induced waveforms are then decoded into the binary value that was originally transmitted. 04736-025 re txd decode encode de decode encode rxd decode encode isolation barrier digital isolation transceiver d r a v dd1 v dd2 gnd 1 gnd 2 b figure 26. adm2483 digital isolation and transceiver sections
data sheet adm2483 rev. c | page 15 of 20 t ruth tables the following truth tables use these abbreviations : letter description h high l evel l low l evel x irrelevant z high i mpedance ( o ff) nc disconnected table 9 . transmitting supply status inputs outputs v dd1 v dd2 de t x d a b on on h h h l on on h l l h on on l x z z on off x x z z off on x x z z off off x x z z table 10 . receiving supply status inputs outputs v dd1 v dd2 a ? b (v) re rx d on on > ? 0. 0 3 l or nc h on on < ? 0.2 l or nc l on on ? 0.2 < a ? b < ? 0. 03 l or nc indeterminate on on inputs o pen l or nc h on on x h z on off x l or nc h off on x l or nc h off off x l or nc l power - up/ p ower - down characteristics the power - up/ power - down characteristics of the adm2483 a re in accordance with the supply thresholds shown in table 11. upo n power - up, the adm2483 o utput signals (a, b , and r x d) reach their correct state once both supplies exc eed their thresholds. upo n power - down, the adm2483 output signals retain their correct state until at least one of the supplies drops below its power - down threshold. when the v dd1 power - down th reshold is crossed, the adm2483 output signals reach their unpowere d states within 4 s. table 11. power - up/power - down thresholds supply transition threshold (v) v dd1 p ower -u p 2.0 v dd1 power -d own 1.0 v dd2 power -u p 3.3 v dd2 power -d own 2.4 thermal shutdown the adm2483 contains thermal shutdown circuitry that protects the part from excessive power dissipati on during fault conditions. shorting the driver outputs to a low impedance source can result in high driver currents. the thermal sensing circuitry detects the increase in die temperature under this condition and disables the driver outputs. this circuitry is designed to disable the driver outputs when a die temperature of 150c is reached. as the d evice cools, the drivers are re - enabled at a temperature of 140c. true fail - safe r eceiver i nputs the receiver inputs have a true fail - safe feature , which ensure s that the receiver output is high when the inputs are open or shorted . during line - idle conditions, when no driver on the bus is enabled, the voltage across a terminating resistance a t the receiver input decay s to 0 v. with traditional transceivers , recei ver input thresholds specified between ?200 mv and +200 mv mean that external bias resistors are required on the a and b pins to ensure that the receiver output s are in a known state. the true fail - safe receiver input feature eliminates the need for bias r esistors by specifying the receiver input threshold between ? 30 mv and ? 200 mv. the guaranteed negative threshold means that when the voltage between a and b decays to 0 v, the receiver output is guaranteed to be high. magnetic field immun ity because i coup lers use a coreless technology, no magnetic components are present , and the problem of magnetic saturation of the core material does not exist. therefore, i couplers have essentially infinite dc field immunity. the analysis that follows defines the conditio ns under which this might occur. the adm2483 s 3 v op erating condition is examined because it represents the most susceptible mode of operation. the limitation on the i coupler s ac magnetic field immunity is set by the condition in which the induced error voltage in the receiving coil (the bottom coil in this case) is made sufficiently large, either to falsely set or reset the decoder. the voltage induced acr oss the bottom coil is given by ; 2 n r dt d v ? ? ? ? ? ? d ? = n n , ... , 2 , 1 = where if the pulses at the transformer output are greater than 1.0 v in amplitude : d = magnetic flux density (gauss) n = number of turns in receiving coil r n = radius of nth turn in receiving coil (cm) the decoder has a sensing threshold of about 0.5 v; therefore, there is a 0.5 v margin in which induced voltages can be tolerated.
adm2483 data sheet rev. c | page 16 of 20 given the geometry of the receiving coil and an imposed requirement that the induced v oltage is, at most, 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field is calculated, as shown in figure 27. 100.000 10.000 1.000 0.100 0.010 0.001 1k 10k 100k 1m 10m 100m 04736-027 magnetic field frequency (hz) maximum allowable magnetic flux density (kgauss) figure 27 . maximum allowable external magne tic flux density for example, at a magnetic field frequency of 1 mhz, the maximum allowable magnetic field of 0.2 k gauss induces a voltage of 0.25 v at the receiving coil. this is about 50% of the sensing threshold and does not cause a faulty output transi tion. simi larly, if such an event occurs during a transm itted pulse and i s the worst - case polarity , it r educe s the received pulse from > 1.0 v to 0.75 v . this is well above the 0.5 v sensing threshold of the d ecoder. t hese magnetic flux density values are s hown in figure 28, using more familiar quantities such as maximum allowable current flow , at given distances away from the adm2483 transformers. 1000.00 100.00 0.10 1.00 10.00 0.01 1k 10k 100k 1m 10m 100m 04736-028 magnetic field frequency (hz) maximum allowable current (ka) distance = 1m distance = 5mm distance = 100mm figu re 28 . maximum allowable current for various current - to - adm2483 spacings a t combinations of strong magnetic field and high frequency, any loops formed by printed circu it board traces could induce large enough error voltages to trigger the thresholds of succeeding circuitry. to avoid this possibility , care should be taken in the layout of such traces.
data sheet adm2483 rev. c | page 17 of 20 applications information power_valid input to avoid chatter on the a and b outputs caused by slow power- up and power-down transients on v dd1 (>100 s/v), the adm2483 features a power_valid (pv) digital input. this pin should be driven low until v dd1 exceeds 2.0 v. when v dd1 is greater than 2.0 v, the pin should be driven high. conversely, upon power-down, the pv should be driven low before v dd1 reaches 2.0 v. the power_valid input can be driven, for example, by the output of a system reset circuit such as the adm809z, which has a threshold voltage of 2.32 v. 04736-029 v dd1 2.32v t por 2.0v 2.32v 2.0v reset reset adm809z adm2483 v dd1 pv gnd 1 v dd1 figure 29. driving pv with adm809z isolated power supply circuit the adm2483 requires isolated power capable of 5 v at 100 ma to be supplied between the v dd2 and gnd 2 pins. if no suitable integrated power supply is available, a discrete circuit, such as the one in figure 30, can be used. a center-tapped transformer provides electrical isolation. the primary winding is excited with a pair of square waveforms that are 180 out of phase with each other. a pair of schottky diodes and a smoothing capacitor are used to create a rectified signal from the secondary winding. the adp667 linear voltage regulator provides a regulated power supply to the adm2483 s bus-side circuitry. to create the pair of square waves, a d-type flip-flop with complementary q/ q outputs is used. the flip-flop can be connected so that output q follows the clock input signal. if no local clock signal is available, a simple digital oscillator can be implemented with a hex-inverting schmitt trigger and a resistor and capacitor. in this case, values of 3.9 k and 1 nf generate a 364 khz square wave. a pair of discrete nmos transistors, switched by the q/ q flip-flop outputs, conduct current through the center tap of the primary transformer, winding in an alternating fashion. 04736-030 3.9k ? 100nf 1nf 74hc14 v cc 74hc74a pr clr dq clk q bs107a bs107a v cc isolation barrier sd103c 22 ? f sd103c 78253 100nf v cc in out 5v set shdn gnd adp667 v dd1 v dd2 gnd 1 gnd 2 adm2483 v cc figure 30. isolated power supply circuit
adm2483 data sheet rev. c | page 18 of 20 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013-aa 10.50 (0.4134) 10.10 (0.3976) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 7 5 ( 0 . 0 2 9 5 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 45 1.27 (0.0500) 0.40 (0.0157) c oplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 16 9 8 1 1.27 (0.0500) bsc 03-27-2007-b figure 31. 16-lead standard small outline package [soic_w] wide body (rw-16) dimensions shown in millimeters and (inches) ordering guide model 1, 2 data rate (kbps) temperature range package description package option adm2483brw 500 ?40c to +85c 16-lead, wide body soic rw-16 adm2483brw-reel 500 ?40c to +85c 16-lead, wide body soic rw-16 adm2483brwz 500 ?40c to +85c 16-lead, wide body soic rw-16 adm2483brwz-reel 500 ?40c to +85c 16-lead, wide body soic rw-16 eval-adm2483ebz adm2483 evaluation board 1 z = rohs compliant part. 2 a -reel suffix designat es a 13-inch (1,000 unit s) tape-and-reel option.
data sheet adm2483 rev. c | page 19 of 20 notes
adm2483 data sheet rev. c | page 20 of 20 notes ? 200 4 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04736 C0 C 11/ 13 ( c )

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